1. Field of the Invention
The present invention relates to computer systems using a plurality of processors and a processor to peripheral bridge, and more particularly, in preventing memory and/or input-output corruption in the multiple processor computer system when a peripheral device is being configured.
2. Description of the Related Technology
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened up many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers.
A significant part of the ever increasing popularity of the personal computer, besides its low cost relative to just a few years ago, is its ability to run sophisticated programs and perform many useful and new tasks. Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer microprocessor central processing unit ("CPU"). The peripheral devices' data transfer speeds are achieved by connecting the peripheral devices to the microprocessor and associated random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the "Peripheral Component Interconnect" or "PCI." A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; PCI System Design Guide, revision 1.0; and PCI BIOS Specification, revision 2.1. These PCI specifications are available from the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214.
A computer system has a plurality of information (data and address) buses such as a host bus, a memory bus, at least one high speed expansion local bus such as the PCI bus, and other peripheral buses such as the Small Computer System Interface (SCSI), Extension to Industry Standard Architecture (EISA), and Industry Standard Architecture (ISA). The microprocessor of the computer system communicates with main memory and with the peripherals that make up the computer system over these various buses. The microprocessor communicates to the main memory over a host bus to memory bus bridge. The peripherals, depending on their data transfer speed requirements, are connected to the various buses which are connected to the microprocessor host bus through bus bridges that detect required actions, arbitrate, and translate both data and addresses between the various buses.
Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. A representative example of one of these new microprocessors is the PENTIUM PRO.TM. (a registered trademark of Intel Corporation) or P6.
The PENTIUM PRO processor implements a dynamic execution micro-architecture comprising a combination of multiple branch prediction, data flow analysis and speculative execution. A second level cache, advanced programmable interrupt controller, and memory bus controller are integrated into a dual cavity integrated circuit package. Another feature of the PENTIUM PRO processor is built-in direct multi-processing support. This enables up to four PENTIUM PRO processors to be connected in a multi-processor configuration without requiring additional "glue logic" components. In a multi-processor system, bus bandwidths are maximized by including pipelined transactions in which the bus transactions in different bus cycle phases overlap, and some of the transactions may be deferred for later completion. Bus transactions may both overlap and be taken out of order to execute, thus resulting in reduced latency in overall program execution.
A problem exists, however, if a memory or input-output ("I/O") cycle is pipelined after a PCI configuration cycle that changes the memory or I/O mapping, respectively, when the pipelined memory or I/O cycle is decoded and acted upon before the PCI configuration cycle has been completed. The PCI specification allows dynamic configuration of PCI devices which may change the computer system and I/O memory map.
Another example is when a notebook computer is hot-docked to an expansion base, the computer system must run auto-configuration cycles to configure the computer system to include the expansion base components. Thus, any I/O cycles must be held in abeyance until the I/O configuration cycle is complete. Otherwise, I/O devices may be addressed that do not yet exist (until configured), or in case of I/O functions duplicated in the notebook computer and the expansion base, the cycle might be directed to the wrong device (i.e., notebook, when it should be to the expansion base).
What is needed is a way for a multi-processor computer system, with processors which pipeline bus cycles, to assure that memory and/or I/O cycles will run only after a peripheral device configuration cycle has been completed.